1. Field of the Invention
The present invention relates to dynamic random access memory architectures and more particularly, to an architecture having an open bit-line cross-point memory cell layout that electrically behaves as a folded bit-line structure.
2. Description of the Prior Art
The early dynamic random access memory (DRAM) used an open bit-line architecture to provide a cross-point memory cell array as shown in FIG. 1a. The conventional open bit-line architecture 1 includes sense amplifiers 2 and true cross-point memory cells 4 formed at the intersection of bit-lines 6 and word lines 8 on one side of the sense amplifiers 2 and complementary cross-point memory cells 4' formed at the intersection of bit-lines 6' and word lines 8' formed on the other side of sense amplifiers 2. The open bit-line architecture provides high packing density of memory cells and permits a cross-point layout of cell structures that optimizes the available cell matrix space. Several deficiencies in the open bit-line architecture have been recognized which include the presence of differential mode noise that leads to low noise immunity and small sense amplifier pitch that creates sense amplifier layout difficulties. In addition, column decoders, which are arranged on the borders of the DRAM chip, are difficult to position. Moreover, the bit-lines and their complements are located in different substrate wells thus contributing to more bit-line swing noise. Furthermore, alpha-particle sensitivity of the device is increased from the differential mode noise thereby increasing the occurrence of single event upset errors.
The folded bit-line architecture as shown in FIG. 1b was adopted to improve the noise immunity of the device and at the same time provide larger layout pitches for the sense amplifier and decoders. As shown in FIG. 1b, the conventional folded bit-line architecture includes a plurality of sense amplifiers 3 each having a corresponding pair of true and complement bit-lines 5 and 5' extending from one side of the amplifiers 3. Memory cells are formed at the intersection of bit-lines 5 and word lines 7 and bit-lines 5' and word lines 7'. The folded bit-line architecture provides high noise immunity resulting from better noise rejection of common mode noise and relaxed sense amplifier pitch allowing easier implementation of sense amplifiers. In addition, the column decoders can be easily arranged along the border of the cell matrix. Moreover, both true bit-lines and their complements are located in the same substrate well thereby creating common mode noise cancellation of substrate noise. Furthermore, the reduction of alpha-particle sensitivity of the device is achieved since some alpha bits may result in a common mode disturbance. However, the folded bit-line architecture provides lower packing density of memory cells than the open bit-line architecture and also cannot utilize a cross-point layout cell structure resulting in an inefficient use of the cell matrix space.
One attempt in the prior art to provide a DRAM architecture taking the advantages of both the open bit-line and the folded bit-line architectures is described by Shah, et al. entitled "A 4-Mbit DRAM with Trench-Transistor Cell", IEEE J. Solid State Circuits, 21(5) 1986. Shah, et al. disclose a double-ended adapted folded bit-line architecture which uses a segmented bit-line approach. Segments are connected to a second metal global bit-line through segment select transistors. Capacitor imbalance is present and a complicated technique is disclosed whereby various segment select transistors are turned on and off depending on which segment is being read.
Also of interest is the publication in IBM Technical Disclosure Bulletin Vol. 30, No. 11, Apr. 1988 at page 246 which discloses a double-traversing pseudo-folded bit-line architecture that is laid out in a cross-point structure but results in a folded-bit-line type connection to the sense amplifier and column decoders, shown in FIG. 2 of the publication. There is no disclosure of the means for implementing the design to provide a minimum of use of the substrate surface area.
There is a desire to provide a DRAM architecture that utilizes the advantages of both a cross-point memory cell open bit-line architecture and the folded bit-line architecture and that may be easily implemented and readily adapted to the advancing multi-megabit DRAM architectures of the future.